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Chip Scale Review September • October • 2019

[ChipScaleReview.com]

Embedded silicon fan-out solution for 40GHz mmWave

chip packaging

By Li Ma, Linyu Li, Fan Yang, Daquan Yu, Zhiyi Xiao

[Huatian Technology (Kunshan) Electronics Co., Ltd.]

and Tong Tian,

Jia bao Niu

[StorMicro Technologies Co., Ltd.]

ecently, the development of

millimeter-wave (mmWave)

wireless communication has

been fast driven by commercial applications,

such as short-range high-data rate wireless

communication, passive imaging and

automotive radars. The requirements for

these systems are usually high performance,

compact size, high level of integration, and

most importantly, low manufacturing cost.

Fan-out wafer-level packaging (FOWLP)

has emerged as a successful technology to

meet the above-mentioned requirements for

mmWave applications.

FOWLP for mmWave applications

FOWLP has evolved as one of the most

versatile packaging technologies in recent

years and already accounts for a market

value of over 1 billion USD due to its

unique advantages and wide applications.

FOWLP can undoubtedly meet the market

demands for miniaturized package size,

higher performance and integration density,

lower power consumption, and lower

manufacturing cost. The embedded and

fan-out package can provide higher I/O

numbers and eliminates the use of substrates

to gain cost advantages. The technology

also has good electrical performance and

heterogeneous integration capabilities,

which has gained significant attention in

recent years [1,2]. FOWLP volumes have

largely been driven by mobile and consumer

applications (RF, baseband, connectivity,

near-field communication [NFC], power

management integrated circuits [PMIC],

audio codec, microcontrollers [MCU], etc.)

and are now moving to 4G communication,

mmWave, automotive, MEMS/sensor and

Internet of Things (IoT) applications.

Many different types of embedded and

fan-out packages have been developed and

reported for mmWave. Infineon Technologies

f irst developed an embedded device

technology based on a molded reconfigured

wafer, known as embedded wafer-level ball

grid array (eWLB), which is a classic fan-out

packaging for mmWave applications [3,4,5].

The thin-film redistribution layer (RDL) of

the eWLB enables very flexible and highly

customizable package designs. eWLB has the

ability to attain minimum interconnection

length and excellent electrical performance,

but there are some limitations because of its

adoption of molding materials. The STATS

ChipPAC team has used eWLB technology

to develop the 77GHz automotive radar,

which enables superior performance and

Grade 1 automotive reliability [6].

Researchers from imec developed a

77GHz automotive radar RF front-end

EMWLP (embedded molding wafer-level

package) module with through-silicon

vias (TSVs) as the vertical interconnection

[7]. The bare transceiver die and the pre-

fabricated TSV chip are reconfigured to form

a molded wafer through the compression

molding process. The measurement results

match the simulation results very well.

Christopher Beck, et al., reported on a highly

integrated 60GHz radar transceiver for

industrial sensor applications [8].

Advantages of embedded silicon fan-

out technology

Embedded silicon fan-out (eSiFO

®

)

technology was developed, improved

and matured by Huatian Technology.

This package can be viewed as a silicon-

based fan-out structure that provides

more area for wiring f lexibility and

BGA connections, and also is similar to

standard WLP.

The biggest difference between an

eSiFO

®

package and a typical eWLB

package in str ucture is that there is

no epoxy molding compound in the

fan-out area, which is replaced by the

silicon carrier. The eSiFO

®

package also

addresses the cost reduction challenge by

eliminating the use of expensive wafer-

level molding equipment and materials

in the process flow. A production yield of

over 99% has been reported in 2017 for

a single-die product with one layer RDL

[9], which demonstrated the feasibility of

eSiFO

®

in high-volume manufacturing.

The manufacturing process used for

eSiFO

®

is a simple chip-first/face-up

mature wafer-level process. Regarding

i t s p e r f o r ma n c e , e S i FO

®

h a s t h e

following advantages:

• Good electrical performance. It

enables short electrical paths from the

die out to the package and uses high-

resistance silicon because a silicon

carrier can further improve electrical

performance for low-loss millimeter

wave transmission [10].

• Good thermal performance. Because

the thermal conductivity of silicon is

much higher than that of the molding

compound used in the typical eWLB

package, eSiFO

®

has a relatively lower

thermal resistance and its temperature

profile is more uniform [11].

• Multi-chip integration capability.

Different dimensions of cavities

for different chips can be achieved

through a one-step etching process,

so it is easy for eSiFO

®

technology to

implement multi-chip integration.

• 3D system integration capability.

eSi FO

®

is compat ible wit h t he

standard TSV technology to form a

3D vertically-stacked structure [12].

40GHz mmWave chip packaging

using eSiFO

®

An eSiFO

®

package for 40GHz mmWave

applications was designed into a 5.0×5.0mm

package size with a single 1.85×1.22mm

embedded die. In order to improve the

sensing performance and block the signal,

the shielding regions were strategically made.

More than 80% of the area was covered by

a metal layer. A number of approaches were

applied to reduce the internal stress, such

as the thin shielding layer, and the stress

release openings. Altogether, 86 balls of

200μm height were fabricated on the first

RDL. To interconnect the chips and I/Os

R