Chip Scale Review September • October • 2019[ChipScaleReview.com]
to the periphery of the reconstructed chip, one RDL layer is designed
and produced. The minimum L/S is 20μm/20μm, which requires high
accuracy lithography technology.
The manufacturing flow is shown in
First, the silicon wafers containing the shielding layer and silicon
cavities were formed. Second, the thinned known good dies (KGDs)
from device wafers were embedded into the cavities. The narrow
trenches between the chips and sidewalls of the cavities were filled
through a vacuum film lamination process. Meanwhile, the pads
of the embedded die were opened using a lithography process. In
order to improve the performance of the device, the thickness of
the dry film is increased compared to the common eSiFO
. At this
point, a new wafer is reconstructed with no significant differences
from the ones by a standard WLP process. The following process
flow is similar with the WLP processes, such as the RDL formation
and ball drop. The difficulties for the product were how to open the
pads of the embedded die in the RDL process and how to ensure the
continuity of the seed layer in the opening hole (30μm) of the thick
first-passivation layer, which has a high aspect ratio (≥1.5:1).
In this project, a 12-inch blank wafer was used as the carrier
wafer. The metal layer (Cu) is used for a shielding cap so that the
signal cannot transmit to the silicon and be reduced.The 1μm Cu
layer was deposited by physical vapor deposition (PVD) rather than
the Cu plating process because the thickness is enough according
to the electromagnetic simulation results. Additionally, the thick Cu
may cause stress and wafer warpage. Then the cavities were formed
by lithography and the wet-etch metal process. In order to decrease
the stress of the large-area metal layer, the scribe lines were opened.
The cavity formation has two steps, including oxide etch and silicon
etch processes. To avoid the tilt and cracking of die during the pick and
place process, a smooth bottom surface without any salient point is critical
for this product. After process optimization, we found that having no
oxide and no photoresist (PR) residual are essential to enable a smooth
bottom surface after the oxide etch process. Therefore, two effective
measures should be carried out, including the oxygen plasma process after
lithography and the oxide etch process with extra oxide etch cycles. The
cavities were formed using the Bosch process. The specification of the
cavities is 104μmwith a TTV of ±7μm.
Because die attach has a huge influence on the pad exposure and
final yield, it is a significant process needed for 40GHz mmWave chip
packaging that uses eSiFO® technology. We used a dedicated die attach
tool from ASM, called NUCLEUS, for the attachment; the tool has a
high accuracy of ±5μm.
shows the image after attachment. The
die shift and rotation of die attach is below 5μm, which meets the design
The formation of the first passivation layer is another essential step in
the 40GHz mmWave chip packaging process flow. In this production,
we used a vacuum lamination process with the photo-patternable dry
film. The narrow trenches between the dies and sidewalls of the cavities
are completely filled, as shown in
. The dry film material
has a big influence on the warpage and the electrical performance. After
development process optimization, the pads of the embedded chip are
opened completely, as shown in
. As a result, the pads were well
connected with the RDL.
After the first passivation process is formation of the RDL. The RDL
formation includes three main processes: 1) seed layer formation,2)
patterning lithography, and 3) Cu layer plating. A thick seed layer with
a 0.3μm metal Ti layer and a 0.5μm metal Cu layer were deposited by
PVD in order to ensure that the seed layer in the high-aspect ratio hole
maintained continuity. The development of patterning lithography is
The process flow of 40GHz mmWave chip packaging.
The whole wafer image after the die attach process.
a) The optical microscopy image after the first passivation process; b)
The optical microscopy image with CD dimension; c) the cross-sectional SEM image
of the filled trench filling and the first passivation layer; and d) the SEM image of the
first RDL metal connecting the pads on the embedded chip.