Chip Scale Review September • October • 2019[ChipScaleReview.com]
The present study was f inancially
suppor ted by t he Nat ional Science
and Technology Major Project No.
1.Fa n - ou t wa r s b eg i n ,” h t t p s: // semiengineering.com/fan-out-wars- begin
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With respect to the sweep frequency
and power consumption, the chip has
obvious superiority. Its applications include
intelligent traffic systems, security systems
and unmanned aerial vehicles.
A mmWave (40GHz) package based on
technology has been successfully
demonst rated and discussed in this
ar ticle. Among the attributes of the
technology are its metal shielding layer
and a thick polyimide (PI) layer on the
surface of the die that provides excellent
electrical performance. Compared to
other wafer-level fan-out technologies,
is a manufact uring friendly
technology, because a wafer that uses
it does not differ significantly from a
standard silicon wafer. In combination
with its elimination of the wafer-level
molding process and materials, eSiFO
also a highly cost-competitive technology.
All these advantages make an attractive
choice for various applications.
CPMT Symp. Japan, 2010 IEEE.
6. D. Wang, et al., “Advanced EWLB
(embedded wafer-level ball grid array)
solutions for mmWave applications,”
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“Embedded wafer-level packaging for
77-GHz automotive radar front-end
with through-silicon via and its 3-D
integration,” IEEE Trans. on Comp.
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“Industrial mmWave radar sensor in
embedded wafer-level BGA packaging
technology,” IEEE Sensors Jour., 2016,
9. D. Yu, et al., “Embedded Si fan-out:
a low cost wafer-level packaging
technology without molding and de-
bonding processes,” Proc. 67th Elec.
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lines on surface stabilized h
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11. D. Yu, “Embedded silicon fan-out
) technology for wafer-level
Embedded and Fan-out Wafer-level
, Wiley, 2019,
Chap. 8, pp. 169-184.
12. S. Ma, et al., “Embedded silicon fan-
out (eSiFO): a promising wafer-level
packaging technology for multi-chip
and 3D system integration,” ECTC,
2018 IEEE 68th.
Li Ma is the manager of the R&D Department at Huatian Kunshan, China, a division of Hua Tian technology
group. He obtained his PhD from Fudan U., Shanghai, China and has two years of post-doctoral experience at the
Institute of Microelectronics of Chinese Academy of Sciences. He has in-depth experience in R&D, especially in
the areas of embedded silicon fan-out and CMOS image sensor packaging. He has almost 20 issued patents.
Linyu Li is an R&D Engineer in the Huatian Group, Kunshan, China. She received a Master’s degree in
Material Engineering from Shanghai U.
Daquan Yu is the CTO of Huatian Group, Kunshan, China. He received a PhD from Dalian U.
of Technology, China; email:email@example.com
Tong Tian is the CEO and CTO at StorMicro Technologies Co., Ltd., Nantong, China. He received a PhD from Xi’an Jiaotong
U. and was granted the Outstanding Research Award by IME, Singapore. In 2010 he joined SIMIT and was involved in mmWave
and THz research. He held an Associate Editor position at IEEE TCAS II for four years. Currently, his main research areas cover
SiCMOS mmWave single-chip system, SiCMOS RF and analog systems, as well as a human microchip implant system.
Jiabao Niu is an RF engineer at StorMicro Technologies Co., Ltd., Nantong, China. He graduated from Xidian U. with an
MSEE degree. His main research areas are mmWave IC packaging and mmWave antennas.
The test properties of the 40G mmWave product.