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34

Chip Scale Review September • October • 2019

[ChipScaleReview.com]

Overview and outlook for heterogeneous integrations

By John H. Lau

[Unimicron Technology Corporation]

eterogeneous integration

[1] i s def i ned a s u si ng

p a c k a g i n g t e c h n o l og y

to integrate dissimilar chips, photonic

devices, or components (either side by side,

stacked, or both) with different materials

and functions, and from different fabless

design houses, foundries, wafer sizes,

feature sizes and companies into a system

or subsystem. System-in-package (SiP) is

very similar to heterogeneous integration,

except heterogeneous integration is for

finer pitches, more inputs/outputs (I/Os),

higher density, and higher performance. In

general, heterogeneous integration can be

classified as heterogeneous integration on

organic substrates, on silicon substrates,

on fan-out RDL (redistribution-layer)

substrates, and on ceramic substrates.

In this study, examples of these types

of heterogeneous integration are given.

Also, the applications of heterogeneous

i nteg rat ion to package - on-package

(PoP), CMOS image sensor (CIS),

microelectromechanical systems (MEMS),

and a vertical cavity surface emitted

laser/photodiode (VCSEL/PD) detector

are presented. Finally, the trends in

heterogeneous integration are discussed.

Heterogeneous integration on

organic substrates

Today, the most common applications

of heterogeneous integration are on

organic subst rates, or the so-called

SiPs. The assembly methods are usually

s u r f a c e mou n t t e ch nolog y (SMT )

including solder-bumped flip chips with

mass ref low and wire bonding chips

on board. In general, these assembly

methods are for low-end to middle-

end applications, such as smartwatches,

automobiles, smartphones, and many

consumer products.

Figure 1

shows an

example of heterogeneous integration on

a printed circuit board (PCB). It can be

seen that the heterogeneous integration

of four chips and four capacitors are

by the fan-out wafer-level packaging

method [2,3]. The package size is 10mm

x 10mm and has two RDLs. Sixty of

these samples without

underf ill went through

the thermal cycling test—

t h e f a i l u r e l o c a t i o n s

and failu re modes a re

shown i n

Figure 1

(at

814 cycles). It can be seen

that the failure locations

are at the solder joints

under the chip cor ners

with the longest distance

to neutral point (DNP)

and the failure mode is

the cracking of the solder

joint between the package

and the bulk solder.

A n o t h e r e x a m p l e

i s t h e l a t e s t A p p l e

iPhone XS and XS Max

(

F i g u r e 2

). T h e r e a r

SiP (A) is a single-sided

assembly that consists

of the baseband chipset,

a power management IC

(PMIC), etc. The large SiP

(B) on top is a two-sided

assembly that consists

of the A12 chipset, ash

memory, etc. The small

SiP (C) on top is also a

two-sided assembly that

consists of the RF front-

end modules (FEMs). All

the PCBs are substrate-

like PCB.

H e t e r o g e n e o u s

integ ration on organic

s u b s t r a t e s f o r h i g h -

performance applications

h a v e b e e n p r o p o s e d

b y S h i n k o w i t h i t s

i n t e g r a t e d t h i n - f i l m

h i g h - d e n s i t y o r g a n i c

p a c k a g e ( i - T H O P )

substrate [4,5] as shown

in

Figure 3

. It can be

seen that thin-film layers

are built on top of the

b u i l d - u p l a ye r s . T h e

me t a l t h ick ne s s , l i ne

width and spacing of the

H

Figure 1:

Heterogeneous integration of four chips on a PCB.

Figure 2:

Apple’s XS and XS Max iPhones. There are three SiPs

supported by a substrate-like PCB.

Figure 3:

Shinko’s i-THOP organic substrate (thin-film layers on top

of build-up layers) for heterogeneous integration. Metal line width and

spacing as well as thickness = 2µm; diameter and thickness of the Cu

pads are, respectively 25µm and 11.82µm, and are on a 40µm pitch.